1. Field of the Invention
The present invention relates to a silicon carbide semiconductor device having a gate structure whose capacitance is reduced, and to its manufacturing method.
2. Description of the Related Art
Silicon carbide (SiC) material has a band gap approximately three times wider, a dielectric breakdown voltage approximately ten times higher, and a thermal conductivity approximately three times higher than those of conventional silicon (Si) material. Accordingly, a semiconductor device (silicon carbide semiconductor device) manufactured using a silicon carbide substrate is characterized in that the device can operate at higher temperature with lower resistivity compared to that (silicon semiconductor device) manufactured using a silicon substrate. Particularly, in a MOSFET (metal oxide semiconductor field effect transistor) or an IGBT (insulated gate bipolar transistor) as a silicon carbide semiconductor device, losses when current flows and when switching operation is performed can be reduced compared to that as a silicon semiconductor device. Specifically, when operated to switch at a high speed, the MOSFET or the IGBT as a silicon carbide semiconductor device has been found to be more effective in loss reduction than that as a silicon semiconductor device.
By the way, when the MOSFET or the IGBT as a silicon carbide semiconductor device is operated to switch at a high speed, its gate capacitance is important to be reduced.
FIG. 9 is a sectional view illustrating a conventional planar MOSFET having a gate structure in which the gate capacitance is reduced, according to those disclosed, for example, in Japanese Patent Application Publication Laid-Open No. 2002-190594 and No. 2007-59636. Moreover, FIG. 10 through FIG. 14 are explanatory views illustrating a general manufacturing process for the planar MOSFET represented in FIG. 9.
A manufacture process for the conventional planar MOSFET and its structure are explained with reference to FIG. 9 through FIG. 14.
First, an n−-type silicon carbide layer 102 is formed, using a vapor-phase epitaxial growth method, on a surface of an n-type silicon carbide substrate 101. Next, well regions 104 are formed, in selected regions of the silicon carbide layer 102, by ion implantation (indicated by arrows A) of aluminum (Al) as a p-type impurity, using a resist layer 103 as a mask therefor. After the ion implantation, the resist layer 103 is removed (refer to FIG. 10).
Then, source regions 106 are formed, in selected regions of the well regions 104, by ion implantation (indicated by arrows B) of nitrogen (N) or phosphorus (P) as an n-type impurity, using a resist layer 105 as a mask therefor. After the ion implantation, the resist layer 105 is removed (refer to FIG. 11).
Contact regions 108 are formed, so as to contact outer side portions of the source regions 106, by ion implantation (indicated by arrows C) of aluminum (Al) as a p-type impurity, using a resist layer 107 as a mask therefor (refer to FIG. 12).
After the resist layer 107 has been removed, activation annealing is performed (for example, at 1500 degrees C. in argon (Ar) atmosphere for 30 minutes) (refer to FIG. 13).
A gate oxide film 109 is formed, by a thermal oxidation method, on the entire surface of the silicon carbide layer 102. Then, a polysilicon film is formed by a chemical vapor-phase growth method, etc. on the gate oxide film 109, and thereafter, gate electrodes 110 are formed by removing unnecessary portions thereof by a dry etching method, etc., using a resist layer as a mask therefor. In this process, the gate electrodes 110 are not formed over a depletion region 111 that is a portion of the silicon carbide layer 102 sandwiched between the well regions 104 (refer to FIG. 14).
After an interlayer insulating film 112 has been formed by a chemical vapor-phase growth method over the surfaces of the gate oxide film 109 and the gate electrodes 110, unnecessary portions thereof are removed by a dry etching method, etc., using a resist layer as a mask therefor.
A source electrode 113 is formed by a physical vapor-phase growth method, etc. on the surfaces of the exposed contact regions 108, source regions 106, and interlayer insulating film 112 (refer to FIG. 14).
Last, a drain electrode 114 is formed by a physical vapor-phase growth method, etc. on the rear surface of the silicon carbide substrate 101; thus, the planar MOSFET illustrated in FIG. 9 is completed.